1. Field of the Invention
The present invention relates to a device and a method for high-level synthesis for outputting a register transfer level description with an operation level description of a circuit as an input.
2. Description of the Related Art
In designing an LSI, an efficient LSI design technique is required, in accordance with a scale increase of the LSI in recent years. Therefore, such a technique is used as to describe a circuit at an operation level with relatively smaller description quantity than that of a register transfer level, and thereafter to synthesize a register transfer level circuit by a high-level synthesis tool.
In an operation level description, the operation of a circuit is described as sequential processing, by using a programming language such as C language. A register transfer level description is generated from such an operation level description by a high-level synthesis tool. Generally, in the high-level synthesis, processes of a flowchart shown in FIG. 13, as will be described hereinafter, are executed.
Specifically, first, in scheduling step S11, the operation description described as sequential processing is inputted, scheduling of arithmetic operations is then made for improving processing performance, and a method of parallel processing is determined. A data flow graph (DFG), in which a dependence relation between data and arithmetic operations is expressed by a graph, is used in the scheduling.
Next, in resource sharing step S12, in order to reduce a circuit area, sharing of a resource for executing the arithmetic operation in the description of the operation level is performed. The input of the resource at this time is the input according to the arithmetic operation in the operation level description, and therefore a selector for controlling the input of the resource is required.
Finally, in control circuit creation step S13, a control circuit required for realizing the scheduling result is created, and thereafter this control circuit and a data path showing a connection form of the resource are outputted to the outside as a register transfer level (RTL) description.
As described above, dependence analysis of the original operation description is performed, and the data flow graph is extracted through the analysis; however, when the dependence relation of data is complicated for the reason that the operation content of the operation level description is changed by an input value, it is not always possible to perform the dependence analysis for extracting only minimum required data dependence. In such a case, a scheduling result expected by a user cannot be obtained.
In addition, since processing performance of the register transfer level circuit is determined by the scheduling, in some cases, the register transfer level circuit satisfying required performance cannot be created. In such a case, as is proposed in Document 1 (A. A. JERRAYA, I. PARK, K. O'BRIEN, “AMICAL: AN INTERACTIVE HIGH LEVEL SYNTHESIS”, Proceedings of European Conference on Design Automation, 1993), there is a method of performing scheduling in which a user satisfies required performance by using a mechanism capable of changing the scheduling. However, the method of creating the control circuit for operating the circuit according to the scheduling result has a limitation because it depends on the tool. Consequently, the scheduling changeable by the user has a limitation.
In addition, as another method, there is a technique of partially determining the scheduling at the stage of operation level description and reducing the scheduling part by a high-level synthesis tool. FIGS. 14A to 14C are diagrams schematically illustrating the scheduling, and FIG. 14A illustrates a processing relation in the sequential operation. FIG. 14B illustrates a processing relation in the scheduling result of the high-level synthesis. When the processing relation required by the user is as shown in FIG. 14C, what is shown in FIG. 14C should be described in advance in the operation level description (change of the operation level description).
However, in order to express the operation of FIG. 14C, a process A and a process B are required to be expressed as parallel processes. In such a case, a language capable of describing the parallel processes as proposed in Document 2 (Thorsten Grotker, Stan Liao, Grant Martin, Stuart Swan, translated by Masaru Kakimoto, Masamichi Kawarabayashi, Takashi Hasegawa, “System C ni yoru system sekkei” (System design by System C), Maruzen, January 2003) is used. When the operation level circuit is described by using such a language, the mechanism for performing simulation of the parallel processes is required for performing operation verification of the operation level description. Further, since the operation level description is a description in which timing should be considered, the operation level description itself may become complicated in some cases.
As is disclosed in US2002/0053069, when a system is operated by a specific protocol, there is a method in which information regarding the timing is held as a library, with the operation level description defined as a description in which timing is not considered, and the scheduling is made by the high-level synthesis tool based on the timing defined tool in the library. In this case, a circuit that can be applied needs to operate in accordance with a predetermined protocol.
In a case that the synthesis of the register transfer level description is performed based on the operation level description, if the required performance is not satisfied by the circuit synthesized by the high-level synthesis tool, a mechanism that allows the user to intervene in the scheduling is provided in a conventional method, but the range that can be controlled by the user is limited. In this case, therefore, the required performance cannot be sufficiently satisfied after all.
In addition, conventionally, there is a method (change of the operation level description) in which the user determines the scheduling at the stage of operation level description. However, in this method, a special mechanism is required for verifying the operation of the operation level description, and moreover, the operation level description is complicated, so that there is a possibility that the design efficiency deteriorates.
Further, conventionally, there is a method of setting the information regarding the timing as a library, without changing the operation level description. However, in this method, the applicable range is limited, and in this case also, the required performance cannot be sufficiently satisfied.